1. Field of the Invention
The present invention relates to a driving method, and more particularly to a method for driving a display panel.
2. Description of Related Art
Conventionally, in the thin-film transistor liquid crystal display (TFT-LCD) panel, M×N sub-pixels need to use M source lines and N gate lines for controlling. Both M and N are natural numbers. Currently, a new driving technique has been developed, wherein the required source lines are reduced by half and the required gate lines are doubled so as to control a panel with M×N sub-pixels. A panel adopting this new technique is called a half-source-double-gate type panel.
Since M is several times more than N, the advantage derived from adopting the new technique is substantially reducing the number of the output pins which control the source driver chips of the source lines thereby reducing the chip areas and lowering the fabricating cost. Additionally, the new technique can also lower the direct current, and increase the flexibility in the panel layout, such as disposing a chip on the left or right side of the panel.
However, this new type of panel still uses the driving timing of the gate line in the old panel, which results in the phenomenon of vertical bright and dim stripes while displaying the same gray level and thereby lowering the frame quality. A new type of panel adopting the line inversion technique and a common potential of an alternating current as well as a new type of panel adopting the dot inversion technique and a common potential of a direct current are taken as examples to illustrate the present invention in the following. It is assumed that both new types of panels adopt the normally black state at the display mode.
FIG. 1 is a schematic diagram illustrating a half-source-double-gate type panel adopting the line inversion technique. The panel in FIG. 1 also uses an alternating current common potential and includes N scan lines, M/2 source lines and 2N gate lines, respectively indicated as L1-L(N), S1-S(M/2) and G1-S(2N). Each of the scan lines includes M sub-pixels 101 and the displayed colors of adjacent sub-pixels on the same scan line are different from each other. R represents red sub-pixels 101, G represents green sub-pixels 101, and B represents blue sub-pixels 101.
FIG. 2 is the timing diagram of each of the signals in the panel of FIG. 1. The VCOM in FIG. 2 refers to a common potential, and all the other reference labels correspond to those in FIG. 1. It can be known from FIG. 2 that the gate lines G1-G(2N) are sequentially driven one by one, which means adopting the driving timing of the old gate lines and simultaneously transmitting frame data to the corresponding sub-pixels through the source lines in the order of turning on the gate lines. For example, when the gate line G1 is driven to turn on the sub-pixels 101 coupled to the gate line G1, the source lines S1-S(M/2) transmit accordingly the frame data required by the turned-on sub-pixels. When the gate line G2 is driven to turn on the sub-pixels 101 coupled to the gate line G2, the source lines S1-S(M/2) transmit accordingly the frame data required by the turned-on sub-pixels.
Nevertheless, since the line inversion technique is adopted, when the gate lines of the same scan line are driven, the alternating current common potentials will be of the same polarity, as shown in FIG. 3. FIG. 3 is a diagram illustrating the changes in polarity of the common potentials of each of the scan lines and each of the source lines in FIG. 2. Referring to FIG. 3, taking the scan line L1 as an example, when the gate line G1 is driven, the common potential VCOM changes its polarity, and hence can only achieve a stable level after a period of time. When the gate line G2 is driven, the polarity does not need to change and therefore the common potential is always maintained at a stable level of the same polarity. It can be known that the voltage difference between the frame signal and the common potential when the gate line G1 is driven is smaller than the voltage difference between the frame signal and the common potential when the gate line G2 is driven. Thus, the luminance of the sub-pixels turned on by the gate line G1 is smaller than the luminance of the sub-pixels turned on by the gate line G2. Certainly, in reality, when the gate line G1 is driven, the common potential VCOM does not necessarily vary as the waveform shown in FIG. 3. However, to sum it up, the voltage difference between the frame signal and the common potential when the gate line G1 is driven and the voltage difference between the frame signal and the common potential when the gate line G2 is driven are different. Similarly, the same situation also happens to the scan lines L2-L(N). When the driving timing of the old gate lines is adopted, the visual phenomenon of vertical bright and dim stripes would occur.
FIG. 4 is a schematic diagram illustrating a half-source-double-gate type panel adopting the dot inversion technique. The panel of FIG. 4 also adopts a direct current common potential. As to the hardware structure of the panel, it is the same as the hardware structure shown in FIG. 1 and thus is not to be reiterated herein. In order to better illustrate, the source lines S1 and S2 and the gate lines G1-G4 are taken as examples to describe the old operation method, as shown in FIG. 5. FIG. 5 is a diagram showing the changes in polarity of the source lines S1 and S2 and the timing of the gate lines G1-G4 of FIG. 4. N in FIG. 4 may represent the integer 0 or a natural number. If N is 0, 4N+1, 4N+2, 4N+3 and 4N+4 represent respectively the first, the second, the third and the fourth image durations. If N is 1, 4N+1, 4N+2, 4N+3 and 4N+4 represent respectively the fifth, the sixth, the seventh and the eighth image durations. The same applies to all the rest. The gate lines G1-G4 are sequentially driven one by one, which means adopting the driving timing of the old gate lines.
It is found in FIG. 5 that during whichever image duration, when the gate lines G2 and G4 are driven, both source lines S1 and S2 just change polarities, and therefore the levels of the common potential VCOM would be affected at the moment. Taking the 4N+1th image duration as an example, when the gate line G2 is driven, the source lines S1 and S2 just change from the positive to the negative polarity, and thus the level of the common potential on the liquid crystal panel would be slightly pulled to the negative polarity. When the gate line G4 is driven, the polarities of the source lines S1 and S2 just change from negative to positive, and therefore the level of the common potential on the liquid crystal panel would be slightly pulled to the positive polarity. Hence, the voltage differences between the source lines S1, S2 and the common potential VCOM when the gate lines G2 and G4 are driven are smaller than the voltage differences between the source lines S1, S2 and the common potential VCOM when the gate lines G1 and G3 are driven. Similarly, the same situation also arises during the 4N+2th to the 4N+4th image durations. When the driving timing of the old gate lines is adopted, the visual phenomenon of vertical bright and dim stripes would occur.